1. Technical Field
The present invention relates to a semiconductor device such as an IC (integrated circuit) chip, a semiconductor mounting structure for the semiconductor device, and an electro-optical device.
2. Related Art
Generally, electro-optical devices such as liquid crystal display devices have electro-optical panels as electro-optical elements used for display. The electro-optical panel includes a plurality of dot areas (that is, island-shaped areas) that are aligned in a predetermined two-dimensional arrangement, for example, a matrix shape. In each dot area, for example, one pair of electrodes disposed to face each other and an electro-optical material interposed between the one pair of electrodes are included. By applying a predetermined voltage value between one pair of electrodes selected from the plurality of dot areas, the optical state of the electro optical material changes, and accordingly, a desired image can be displayed.
In the electro-optical device, in order to select desired dot areas, a scanning signal is supplied to one of the one pair of electrodes, and a data signal is supplied to the other electrode. The scanning signal and the data signal are generated by a driving circuit having a predetermined circuit configuration. This driving circuit is, for example, formed inside a driving IC that is a semiconductor device. The driving IC is manufactured by performing a known semiconductor manufacturing method, for example, for a silicon wafer. The driving IC may be mounted on a substrate, which is formed of glass or plastic, that forms the electro-optical panel or a relay substrate that is connected to the substrate.
In the substrate or the relay substrate on which the driving IC is mounted, various wirings such as wirings used for supplying a signal and power to the driving IC or wirings used for transferring the scanning signal and the data signal that are generated by the driving IC to the electrodes inside the electro-optical panel are disposed. In the wirings, wiring terminals that are electrically connected to the driving IC are disposed.
Mounting the driving IC on the substrate is, for example, performed by using a flip chip mounting method. The flip chip mounting method is a method in which a connection electrode called a bump is formed on a circuit face, that is, an active face of the driving IC and the connection electrode is conductively connected to a wiring terminal on the substrate. In such a case, the driving IC is in a state in which the driving IC is packaged in an almost same size as a bare chip, that is, a chip-scale packaged state. The semiconductor mounting structure of the chip scale package has been disclosed, for example, in JP-A-2001-223319 (Page No. 4, FIGS. 1 and 2) and Japanese Patent No. 2731471 (Page Nos. 3 to 4, FIG. 1).
In JP-A-2001-223319, technology or conductively connecting a solder bump as a connection electrode to a wiring terminal disposed on the substrate has been disclosed. In addition, in Japanese Patent No. 2731471, an electrical connection structure in which a conductive body layer is formed on a protrusion part formed of a resin and the conductive body layer is brought into direct contact with a wiring terminal disposed on the substrate by using an adhesive agent has been disclosed.
Considering a case where the driving IC having a bare chip size is mounted on a substrate such as a glass substrate, a plurality of connection electrodes of the driving IC is electrically connected to a plurality of wiring terminals disposed on the substrate. The plurality of wiring terminals disposed on the substrate and wirings connected thereto are commonly formed on one face of the substrate by using a photo etching method. Thus, the wirings are needed to be insulated from one another, and it is difficult to form a cross-wiring that intersects a part of a wiring with other wirings in a same photo etching process. In other words, in order to form a cross-wiring, there is a problem that a new process is needed.
In addition, a case where the driving IC is mounted on the substrate and a relay substrate such as an FPC (flexible printed circuit) substrate is connected to the substrate or a case where the driving IC is mounted on the relay substrate will be considered. In such a case, when a cross wiring is to be formed on the relay substrate, generally ordinary wirings are needed to be formed on one face of the relay substrate and a cross wiring is needed to be formed on the other face. As described above, when the relay substrate is formed by using a double-sided wiring, the number of processes increases, and accordingly, there is a problem that the cost for the manufacturing process increases.